1. Field of the Invention
The present invention is directed generally to multi-port random access memories (RAMs) and, more particularly, to a multi-port RAM having multiple operating modes.
2. Description of the Background
RAMs having two or more ports are known as multi-port RAMs. Multi-port RAMs allow two or more devices to share and manipulate a common set of data at the same time. There are several variations of multi-port RAMs such as video RAMs (VRAMs), two and three port RAMs, and RAMs having a combination of random access and sequential access ports, all of which are described in U.S. Pat. No. 4,891,794, issued to Hush et al. and assigned to Micron Technology, Inc., and U.S. Pat. No. 5,450,355, issued to Hush and assigned to Micron Technology, Inc., both of which are hereby incorporated by reference. Multi-port RAMs come in many variations and have many applications.
Multi-port RAMs have the disadvantage that data collisions occur when two or more ports attempt to access the same memory address at the same time. Data collisions often result in corrupt data at the data address where the collision occurs, and as a result, the integrity of the data must be restored, resulting in lost process cycles. To prevent data collisions, access to a multi-port RAM needs to be monitored and controlled. If two or more ports attempt to access the same data address, one port will be given immediate access, and the other port will be given an interrupt signal and forced to wait. Multi-port RAMs can typically determine when a data collision has already occurred, but require the help of external devices to prevent a data collision.
An approach to preventing data collisions in a dual port RAM is described in U.S. Pat. No. 5,454,095, issued to Kraemer et al. A dual port RAM is divided into two regions with one port having read only access to one region and write only access to the other region, while the other port has the opposite privileges. That alone, however, does not prevent data collisions, so the ports are further restricted such that both must perform the same function, either a read or a write, at the same time. Although those devices successfully eliminate data collisions without the need for external devices, they limit the usefulness of the dual port RAMs.
Expanding a memory array using multi-port RAMs is often a complex procedure. Most multi-port RAMs come in two variations, a master and a slave. In a memory array there must be only one master, and the remainder slaves. The master monitors the addresses being accessed by each port, and with the help of external devices, may provide an interrupt signal to prevent data collisions. In that way, if a potential data collision is sensed, the master decides which port may access the memory address immediately and which port or ports must wait. If more than one master is used, there may be conflicting decisions between the masters so that one master inhibits one port, while another master inhibits the other port, resulting in neither port gaining access to the RAM. Thus, the need exists to provide a multi-port RAM which has the capability to avoid collisions without the need for external devices. The need also exists for a multi-port RAM architecture which avoids the master/slave functions such that expansion can be easily accomplished.